Design Idea

Current Sensing LDO Voltage Regulator

 

John Stoughton

November 3, 1997

 

When designing battery operated devices, battery contact chatter can be a difficult problem to overcome.  When chatter occurs at a critical time, the results can be devastating.  For instance, if a memory write occurs when this interruption in power occurs, memory corruption can occur, checksums may be computed wrong or may not be written at all.

 

A great tool in the arsenal of battery powered device designers has been the low drop out (LDO) regulator.  Briefly, these regulators use PNP devices for their output devices and as a result, have drop out voltages (V_IN-V_OUT while still in regulation) that equal the VCE|_SAT of the PNP rather than a couple of VBE drops.  For example, the LP2951 has a drop out voltage (at IOUT=100mA) of 600mV while the drop out voltage of a LM317L is almost 2 volts under the same conditions.  This feature of LDO regulators allows the designer to use another volt of end of life battery potential.

 

Several manufacturers of regulators have pins on their devices that signal a power error condition.  The circuits that I am aware of look at the output of the IC and signal if the output falls out of bounds (see FIGURE ONE).  This is after the fact error detection.  By the time that the mP sees the warning, the output (by definition) is already out of specification.  In the ubiquitous LP2951 the error pin goes low only after the output is already 7.5%  below its nominal output voltage.  Many logic devices call for regulation within ±5% of nominal.  The problems with this kind of error sensing are many and obvious.

 

The invention proposed here (see FIGURE TWO) senses interruptions in regulator input current instead of output voltage.  This is a more proactive error detection scheme than sensing output voltage.  The input current interruption can be sensed while the output voltage is still within regulation.  This saves precious milliseconds.  This time can be used to do those emergency “clean up” tasks that are required for a safe shutdown while the regulator’s output voltage is still within specification.

 

To do this current sensing, a second PNP transistor (Q2) has been added (in a current mirror configuration) to the pass PNP of the classical LDO topology.  The transistor would be scaled so that Q2 conducts a fraction of the current that flows through Q1 in order to limit power consumption.  It is also possible that R2 could be sized such that the transistor is normally in saturation (minimizing the power dissipation of this transistor and load).  The voltage across this load resistor is compared to a known voltage (VREF 2 in the accompanying schematic).  If this voltage is lower than VREF 2 then the /ERROR pin goes low signifying an error event.

 

What distinguishes this from the standard ERROR signal from other LDO regulators is that the output has not begun to fall at the point the error signal is generated.  If one knows how long it takes to finish the longest critical event that the mP has, it is easy to size the post regulator filter capacitor to keep the voltage drop over this time to an acceptable level.  The battery powered device then can do whatever is required to put the instrument to “sleep” while minimizing the potential for serious instrument malfunctions.  This could include the computation and writing of a checksum to an EEPROM. 

 

In practice, one would probably want to keep the output voltage sensing of the conventional LDO circuit.  Otherwise the voltage could drop out of regulation with no error detection.  The outputs of the two error detection circuits (current sensing and output voltage sensing) could be combined.  The LP2951 output is an open collector.  If the current sensing circuitry was added to this IC, the collectors of the two comparators could be connected.  Other enhancements could be include a pulse stretching circuit or latch on the error output.  There are lots of possibilities.